\section{Test templates description}

Test template defines properties of future test program. Test
template contains sequence of instructions. Each element of this
sequence has instruction name, arguments (registers, addresses,
values) and test situation (relation between values of arguments and
microprocessor state before execution of instruction). Example of
test template description for model instruction set:

REGISTER reg1 : 32;

REGISTER reg2 : 32;

ADD reg1, reg2, reg2

LOAD reg1, reg2 @ l1Miss, l2Hit

SUB reg2, reg1, reg2

This template has 3 instructions -- ADD, LOAD and SUB. Template
begins from variable definitions (it has name of variable and its
bit length). Test situation is specified after "@": test situation
of the second instruction is "l1Miss, l2Hit": "l1Miss" means cache
miss in first-level cache and "l2Hit" means cache hit in
second-level cache.

Model instruction set contains only 2 memory operation:
\begin{itemize}
\item "LOAD reg, address" loads value from memory by physical address
"address" to the register "reg";
\item "STORE reg, address" stores value from register "reg" to the
memory by physical address "address".
\end{itemize}

Test data generation is generation of initial values of registers
and initial contents of cache-memory. This problem has been solved
for common microprocessor cache-memory. The following consists of
test data generation for 2 basis cache-memory organizations: fully
associative cache with LRU and direct mapped cache. Common cache
includes aspects from both cache-memory organizations. The rest of
paper deals with one-level cache-memory although proposed method can
be applied to cache memory with more than one level.
